DK-DEV-5SGXEA7N【PDF 104/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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4-34

Clock Multiplication and Division

SV51005

2014.01.10

Table 4-7: Example of the PLL Grouping for Stratix V GX A5 and A7 Devices, and Stratix V GT C5 and C7 Devices

PLL Section

First Group

PLL Location

Second Group

Upper left

Lower left

FRACTIONALPLL_X0_Y122 , FRACTIONALPLL_ FRACTIONALPLL_X0_Y100 , FRACTION-

X0_Y113 , FRACTIONALPLL_X0_Y66 ALPLL_X0_Y91 , FRACTIONALPLL_X0_Y75

FRACTIONALPLL_X0_Y53 , FRACTIONALPLL_ FRACTIONALPLL_X0_Y44 , FRACTION-

X0_Y10 , FRACTIONALPLL_X0_Y1 ALPLL_X0_Y29 , FRACTIONALPLL_X0_Y20

FRACTIONALPLL_X210_Y122 ,

FRACTIONALPLL_X210_Y100 ,

Upper right

Lower right

FRACTIONALPLL_X210_Y113 ,

FRACTIONALPLL_X210_Y66

FRACTIONALPLL_X210_Y53 ,

FRACTIONALPLL_X210_Y10 ,

FRACTIONALPLL_X210_Y1

FRACTIONALPLL_X210_Y91 , FRACTION-

ALPLL_X210_Y75

FRACTIONALPLL_X210_Y44 , FRACTION-

ALPLL_X210_Y29 , FRACTIONALPLL_

X210_Y20

Clock Multiplication and Division

Each Stratix V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The

input clock is divided by a pre-scale factor, N , and is then multiplied by the M feedback factor. The control

loop drives the VCO to match f in × (M/N).

The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency,

multiplication, and division values entered into the ALTERA_PLL megafunction.

VCO Post Divider

A VCO post divider is inserted after the VCO. When you enable the VCO post divider, the VCO post divider

divides the VCO frequency by two. When the VCO post divider is bypassed, the VCO frequency goes to the

output port without being divided by two.

Post-Scale Counter, C

Each output port has a unique post-scale counter, C , that divides down the output from the VCO post divider.

For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the

output frequencies that meets its frequency specifications. For example, if the output frequencies required

from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz (the least common

multiple of 33 and 66 MHz within the VCO range). Then the post-scale counters, C , scale down the VCO

frequency for each output port.

Pre-Scale Counter, N and Multiply Counter, M

Each PLL has one pre-scale counter, N , and one multiply counter, M , with a range of 1 to 512 for both M and

N . The N counter does not use duty-cycle control because the only purpose of this counter is to calculate

frequency division. The post-scale counters have a 50% duty cycle setting. The high- and low-count values

for each counter range from 1 to 256. The sum of the high- and low-count values chosen for a design selects

the divide value for a given counter.

Altera Corporation

Clock Networks and PLLs in Stratix V Devices

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